SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.3
3.3.1
Clock Considerations
The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the 32.768-KHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the
state of the CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot
change dynamically after reset.
In addition, the DSP requires a reference clock for USB applications. The USB reference clock is
generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI
and USB_MXO pins.
The USB reference clock is not required if the USB peripheral is not being used. To completely disable the
USB oscillator, connect the USB_MXI pin to ground (V SS ) and leave the USB_MXO pin unconnected. The
USB oscillator power pins (USB_V DDOSC and USB_V SSOSC ) should also be connected to ground.
The RTC oscillator generates a clock when a 32.768-KHz crystal is connected to the RTC_XI and
RTC_XO pins. The 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP.
However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers
(I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management
register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator,
connect the RTC_XI pin to CV DDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 5.4 , External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins .
Clock Configurations After Device Reset
After reset, the on-chip Bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin. If CLK_SEL = 0, the Bootloader programs the system clock generator and sets the
system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the
Bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN
pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. While
the bootloader tries to boot from the USB, the clock generator will be programmed to output approximately
36 MHz.
3.3.1.1
Device Clock Frequency
After the boot process is complete, the user is allowed to re-program the system clock generator to bring
the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not).
The user must adhere to various clock requirements when programming the system clock generator. For
more information, see Section 5.5 , Clock PLLs .
Note: The on-chip Bootloader allows for DSP registers to be configured during the boot process.
However, this feature must not be used to change the output frequency of the system clock generator
during the boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling
time. The bootloader register modification feature must not modify the Timer0 registers.
52
Device Configuration
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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